A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension 104 and a source extension 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension 104 and the source extension 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate structure 118 which may be a polysilicon gate. A gate silicide 120 is formed on the polysilicon gate 118 for providing contact to the polysilicon gate 118. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where a MOSFET is fabricated therein.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the polysilicon gate 118 and the gate oxide 116. When the spacer 122 is comprised of silicon nitride (SiN), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the polysilicon gate 118 and the gate oxide 116.
Referring to FIG. 1, dopant implanted into the drain contact junction 108 and the source contact junction 112, which are deeper junctions, and the gate structure 118 are activated typically using a RTA (Rapid Thermal Anneal) process at a relatively higher temperature such as at temperatures greater than 1000.degree. Celsius, for example, as known to one of ordinary skill in the art of integrated circuit fabrication. Such higher temperature activation in the deeper drain and source contact junctions 108 and 112 reduces silicide to contact junction resistance. In addition, such higher temperature activation in the gate structure 118 reduces poly-depletion effect within the gate structure 118 such that the speed performance of the MOSFET 100 is enhanced, as known to one of ordinary skill in the art of integrated circuit fabrication.
In contrast, as dimensions of the MOSFET 100 are scaled further down to tens of nanometers, the drain extension 104 and the source extension 106 are desired to be abrupt and shallow junctions to minimize short-channel effects of the MOSFET 100, as known to one of ordinary skill in the art of integrated circuit fabrication. In addition, for enhancing the speed performance of the MOSFET 100 with scaled down dimensions, a high dopant concentration in the drain extension 104 and the source extension 106 is desired.
In the prior art, dopant within the drain extension 104 and the source extension 106 are activated using a RTA (Rapid Thermal Anneal) process at a relatively lower temperature such as at temperatures less than 1000.degree. Celsius, for example, as known to one of ordinary skill in the art of integrated circuit fabrication. However, as dimensions of the MOSFET 100 are further scaled down, a RTA process is disadvantageous because thermal diffusion of the dopant within the drain extension 104 and the source extension 106 causes the drain extension 104 and the source extension 106 to become less shallow. In addition, with a RTA process, the concentration of the dopant within the drain extension 104 and the source extension 106 is limited by the solid solubility of the dopant within the drain extension 104 and the source extension 106, as known to one of ordinary skill in the art of integrated circuit fabrication.
Because of such limitations of using a RTA process to activate dopant within the drain extension 104 and the source extension 106, a laser thermal process is proposed in the technical journal article, Ultra-Shallow, Abrupt, and Highly-Activated Junctions by Low-Energy Ion Implantation and Laser Annealing by Somit Talwar et al., SPIE 1998, pages 74-77. In such a laser thermal process, the dopant within the drain extension 104 and the source extension 106 is activated by directing a laser beam toward the drain extension 104 and the source extension 106.
Activation by such a laser thermal process is advantageous because the time period for heating the drain extension 104 and the source extension 106 is on the order of a few nanoseconds (which is approximately eight orders of magnitude shorter than a RTA process). Thus, thermal diffusion of dopant within the drain extension 104 and the source extension 106 is negligible such that the drain extension 104 and the source extension 106 remain shallow, as known to one of ordinary skill in the art of integrated circuit fabrication.
In addition, because the semiconductor material forming the drain extension 104 and the source extension 106 becomes molten and then recrystallizes, the drain extension 104 and the source extension 106 formed by activation using the laser thermal process is an abrupt junction. Furthermore, because the melting and recrystallization time period is on the order of hundreds of nanoseconds, the activated dopant concentration within the drain extension 104 and the source extension 106 is well above the solid solubility, as known to one of ordinary skill in the art of integrated circuit fabrication.
Despite such advantages of the laser thermal process, the drain extension 104 and the source extension 106 formed using the laser thermal process may also have several disadvantageous features. Referring to FIG. 2, a MOSFET 200 has a drain extension 130 and a source extension 132 formed by using the laser thermal process. (Elements having the same reference number in FIGS. 1 and 2 refer to elements having similar structure and function.)
For forming the drain extension 130 and the source extension 132, the spacer 122 is etched. However, the spacer liner oxide 124 which is relatively thin (typically in the range of 100 .ANG. (angstroms) to 200 .ANG. (angstroms) for example), typically remains on the sidewalls of the gate structure 118. Because the drain extension 130 and the source extension 132 formed by activation using the laser thermal process is an abrupt junction, the drain extension 130 and the source extension 132 may not sufficiently extend under the gate structure 118 because of the off-set from the spacer liner oxide 124 remaining on the sidewalls of the gate structure 118. Such insufficient overlap of the gate structure 118 over the drain extension 130 and the source extension 132 results in large series resistance at the drain and source of the MOSFET 200 and in degradation of the speed performance of the MOSFET 200.
Furthermore, because the drain extension 130 and the source extension 132 formed by activation using the laser thermal process is an abrupt junction, as the channel length of the MOSFET 200 is scaled down to tens of nanometers, subsurface punch-through effects in the channel region 134 of the MOSFET 200 results in leakage current in the MOSFET 200.
Nevertheless, as the MOSFET is further scaled down, a laser thermal process for activating dopant in the drain extension and the source extension of the MOSFET is desired for fabrication of drain and source extensions that are shallow and abrupt junctions with high concentration of dopant. Thus, a process is desired for fabricating shallow and abrupt drain and source extensions with high concentration of dopant using the laser thermal process while at the same time minimizing the high series resistance at the drain and source of the MOSFET and minimizing the high leakage current that may result.